1. Field Of The Invention
This invention relates generally to computer networks, and in particular to a fault tolerant network having a semaphore box for controlling access to shared peripherals by a plurality of computers.
2. Description of Related Art
Multiprocessor systems typically include some method of providing interprocessor communication. For example, interprocessor communication through a shared main memory is typically referred to as a "loosely coupled" computer system. Interprocessor communication through shared registers is typically referred to as a "tightly coupled" computer system. Prior patent of the Assignee of the present invention, Cray Research, Inc., disclose various forms of interprocessor communication.
One such prior patent is U.S. Pat. No. 4,636,942, issued Jan. 13, 1987, to Chen et al., which patent is incorporated herein by reference. This patent discloses a computer vector multiprocessing control wherein a pair of processors are provided and each are connected to a central memory through a plurality of memory reference ports. Processors are further connected to a plurality of shared registers, including registers for holding scalar and address information, and registers for holding information to be used in coordinating the transfer of information through the shared registers.
Another prior patent is U.S. Pat. No. 4,661,900, issued Apr. 28, 1987, to Chen et al., which patent is incorporated herein by reference. This patent discloses a flexible chaining method and apparatus wherein a part of processors are connected to a central memory through a plurality of memory reference ports. The processors are connected to a plurality of shared registers that may be directly addressed by either processor, and which hold scalar and address information in registers for holding information to be used in coordinating the transfer of information through the shared registers.
Still another prior patent is U.S. Pat. No. 4,754,398, issued Jun. 28, 1988, to Pribnow, which patent is incorporated herein by reference. This patent discloses an interprocessor communication system for a multiprocessor system that includes a plurality of clusters having a plurality of semaphore registers and information registers.
Whatever the merits of these prior patents for controlling interprocessor communication, they do not achieve the benefits of the present invention.